1. Field of the Invention
The present invention relates to complementary MOS circuits and specifically to a method for providing a high-speed interconnection between semiconductor chips incorporating complementary MOS circuits, despite the high internal impedance of the MOS transistors.
2. The Prior Art
Semiconductor circuits incorporating complementary MOS transistors are recognized as having desirable characteristics, among which is their relatively low power consumption. A disadvantage of such circuits, however, derives from their relatively slow speed of operation in many cases, due to the relatively high internal impedance of the MOS transistors. The high internal impedances do not permit a rapid charging of the capacitance associated with a connecting line interconnecting an output of one complementary MOS circuit with the input of another complementary MOS circuit, and connecting lines having low characteristic impedances cannot be used effectively because of the relatively high voltage levels characteristic of the complementary MOS circuits. Although it is known in the art to use relatively low impedance transistors as output stages, such transistors occupy a very large space and therefore interfere with the achievement of maximum density of components on the semiconductor chips.